IBM Announces Sub-1 Nanometer Chip Technology
IBM 宣布推出小於 1 奈米的晶片技術
更新於: 2026年7月25日 上午03:30
On June 25, 2026, IBM announced a groundbreaking leap in semiconductor engineering with the introduction of the world's first sub-1 nanometer (nm) chip technology.
2026年6月25日，IBM宣布在半導體工程領域取得突破性進展，推出了全球首款小於1奈米（nm）的晶片技術。
Operating at the 0.7 nm node—or 7 angstroms—this advancement marks our transition into the 'Angstrom era,' where components are only a few atoms wide.
該技術運作於0.7奈米節點（即7埃），這標誌著我們邁入「埃米時代」，此時的組件寬度僅有幾個原子大。
Central to this achievement is the 'nanostack' architecture.
此項成就的核心在於「奈米堆疊」架構。
Unlike traditional 2D designs, this 3D approach stacks transistors vertically, allowing nearly 100 billion of them to fit on a chip the size of a fingernail.
與傳統的2D設計不同，這種3D方法將電晶體垂直堆疊，使將近1000億個電晶體能安裝在指甲大小的晶片上。
Beyond mere size, the performance benefits are significant.
除了尺寸之外，效能優勢也非常顯著。
IBM projects up to 50% higher performance and 70% greater energy efficiency compared to its previous 2 nm models.
IBM預計，與其先前的2奈米型號相比，效能將提升高達50%，能源效率則提升70%。
This technology also enhances SRAM density by 40%, which is essential for handling the heavy data loads required by modern generative AI and cloud infrastructure.
此技術還將靜態隨機存取記憶體(SRAM)的密度提高了40%，這對於處理現代生成式AI和雲端基礎建設所需的大量數據負載至關重要。
While currently a research milestone, IBM aims to bring this technology to commercial production within the next five years.
儘管目前僅為研發里程碑，IBM目標在未來五年內將此技術投入商業化生產。
By utilizing innovative fabrication techniques, this development provides a vital roadmap for continued computing growth for at least the next decade.
透過運用創新的製造技術，此開發成果為未來至少十年的計算成長提供了一條關鍵的路線圖。
